基本邏輯閘
74138(3 to 8)解碼器
七段顯示器之解碼電路
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--實驗名稱：基本邏輯閘實習
--檔案名稱：logic.vhd
--功 能：SW1 -> and, SW2 -> or, SW3 -> xor, SW4 -> nand
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity logic is
port(
A : in std_logic_vector(3 downto 0); --輸入訊號 A
B : in std_logic_vector(3 downto 0); --輸入訊號 B
SEL : in std_logic_vector(3 downto 0); --選擇訊號 SEL
C : out std_logic_vector(3 downto 0) --輸出訊號 c
);
end logic;
architecture a of logic is
begin
---------- 選擇邏輯運算子 ----------
process(A,B,SEL)
begin
case SEL is
when "1110" => --按下SW1，做AND運算
C <= A and B;
when "1101" => --按下SW2，做OR運算
C <= A or B;
when "1011" => --按下SW3，做XOR運算
C <= A xor B;
when "0111" => --按下SW4，做NAND運算
C <= A nand B;
when others => --其他情況下LED不亮
C <="0000";
end case;
end process;
end a;
--實驗名稱：74138(3 to 8)解碼器實習
--檔案名稱：TTL74138.vhd
--功 能：3對 8解碼器電路描述
Library IEEE;
Use IEEE.std_logic_1164.all;
Entity TTL74138 is
port ( A,B,C: in STD_LOGIC;
G1: in STD_LOGIC;
G2A,G2B: in STD_LOGIC;
Y: out STD_LOGIC_vector(7 downto 0) );
end TTL74138;
Architecture a of TTL74138 is
signal XIN : std_logic_vector(5 downto 0);
begin
XIN <= G1 & G2B & G2A & C & B & A;
with XIN select
Y <= "11111110" when "100000",
"11111101" when "100001",
"11111011" when "100010",
"11110111" when "100011",
"11101111" when "100100",
"11011111" when "100101",
"10111111" when "100110",
"01111111" when "100111",
"11111111" when others;
end a;
--實驗名稱：七段顯示器之解碼電路實習
--檔案名稱：sevseg_UP1.vhd
--功 能：低電位驅動之七段顯示器實習
library ieee;
use ieee.std_logic_1164.all;
entity sevseg_UP1 is
port( x:in std_logic_vector(3 downto 0);
y:out std_logic_vector(6 downto 0);
comm:out std_logic);
end sevseg_UP1;
architecture a of sevseg_UP1 is
begin
comm<='1';
with x select
y <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when "1111",
"1111111" when others;
end a;
--實驗名稱：74147優先編碼器實習
--檔案名稱：Encoder74147.vhd
--功 能：實現優先編碼器電路動作
library ieee;
use ieee.std_logic_1164.all;
entity Encoder74147 is
port ( A: in std_logic_vector(1 to 9);
Y: out std_logic_vector(3 downto 0));
end Encoder74147;
architecture a of Encoder74147 is
begin
Y<="0110" when A(9)='0' else
"0111" when A(8)='0' else
"1000" when A(7)='0' else
"1001" when A(6)='0' else
"1010" when A(5)='0' else
"1011" when A(4)='0' else
"1100" when A(3)='0' else
"1101" when A(2)='0' else
"1110" when A(1)='0' else
"1111";
end a;
--實驗名稱：全加法器實習
--檔案名稱：full_add.vhd
--功 能：全加法器電路描述
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY full_add IS
PORT ( SA,SB,SCin :in bit;
Scout:out bit;
Sum:out bit);
END full_add;
ARCHITECTURE a OF full_add IS
BEGIN
Sum <= SA xor SB xor SCin;
Scout<=(SA and SB) or (SB and SCin) or (SCin and SA);
END a;
--實驗名稱：四位元加法器實習
--檔案名稱：full_add4.vhd
--功 能：四位元加法器電路描述
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY full_add4 IS
PORT ( A,B :in bit_vector(3 downto 0);
cin:in bit;
sum:out bit_vector(3 downto 0);
cout:OUT bit);
END full_add4;
ARCHITECTURE a OF full_add4 IS
component FULL_ADD
port(SA,SB,SCin:in bit;
Scout,SUM:out bit);
end component;
signal CARRY:bit_vector(4 downto 0);
BEGIN
CARRY(0)<=cin;
G1:for I in 3 downto 0 generate
FA:FULL_ADD port map (CARRY(I),A(I),B(I),CARRY(I+1),SUM(I));
end generate G1;
cout<=CARRY(4);
END a;
--實驗名稱：三位元乘法器實習
--檔案名稱：mul3.vhd
--功 能：三位元乘法器電路描述
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mul3 is
port ( a,b:in std_logic_vector(2 downto 0);
x:out std_logic_vector(5 downto 0));
end mul3;
architecture a of mul3 is
signal temp1:std_logic_vector(2 downto 0);
signal temp2:std_logic_vector(3 downto 0);
signal temp3:std_logic_vector(4 downto 0);
begin
temp1<=A when b(0)='1' else "000";
temp2<=(A&'0') when b(1)='1' else "0000";
temp3<=(A&"00") when b(2)='1' else "00000";
x<=temp1+temp2+('0'&temp3);
end a;
74147優先編碼器
全加法器
四位元加法器
三位元乘法器