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---------------------------------------------------------------------
--實驗名稱：基本ALU實習
--檔案名稱：alu.vhd
--功能：Case-when敘述完成簡單ALU電路描述
---------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY alu IS
PORT ( M: in std_logic;
s: IN STD_LOGIC_VECTOR(1 downto 0);
A,B:IN STD_LOGIC_VECTOR(2 downto 0);
F:OUT STD_LOGIC_VECTOR(2 downto 0));
END alu;

ARCHITECTURE a OF alu IS
BEGIN
process(s,A,B)
Begin
IF M='0' then
Case s IS
When "00"=>
F<=A;
When "01"=>
F<=A and B;
When "10"=>
F<=A or B;
When others=>
F<=Not A;
END case;
ELSE
Case s IS
When "00"=>
F<=A+B;
When "01"=>
F<=A-B;
When "10"=>
F<=A+1;
When others=>
F<=A-1;
End case;
end if;
End Process;
END a;

-----------------------------------------------------------------------------------------
--實驗名稱：可由1.842Mhz除頻產生8Hz,4Hz,2Hz和1Hz的除頻器
--檔案名稱：clk_div.vhd
--功能：clk_out = clk_in / divisor
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clk_div is
generic(divisor:integer:=230400);
--generic(divisor:integer:=17);
port(
clk_in : in std_logic;
clk_out8Hz: buffer std_logic;
clk_out4Hz: buffer std_logic;
clk_out2Hz: buffer std_logic;
clk_out1Hz: buffer std_logic
);
end clk_div;

architecture arch of clk_div is
signal cnt2 : std_logic;
begin
---------- clk divider ----------
process(clk_in)
variable cnt1,divisor2 : integer range 0 to divisor;
begin
divisor2:=divisor/2;
----- up counter -----
if (clk_in'event and clk_in='1') then
if cnt1 = divisor then
cnt1 := 1;
else
cnt1 := cnt1 + 1;
end if;
end if;
----- clk_out register clk generator -----
if (clk_in'event and clk_in='1') then
if (( cnt1 = divisor2) or (cnt1 = divisor))then
cnt2 <= not cnt2 ;
end if;
end if;
clk_out8Hz <= cnt2 ;
end process;

process(clk_out8Hz)
begin
if clk_out8Hz'event and clk_out8Hz='1' then
clk_out4Hz <= not(clk_out4Hz);
end if;
end process;

process(clk_out4Hz)
begin
if clk_out4Hz'event and clk_out4Hz='1' then
clk_out2Hz <= not(clk_out2Hz);
end if;
end process;

process(clk_out2Hz)
begin
if clk_out2Hz'event and clk_out2Hz='1' then
clk_out1Hz <= not(clk_out1Hz);
end if;
end process;

end arch;

------------------------------------------------------------------------------
--實驗名稱：可選擇四個不同輸入頻率之上數計數器電路
--檔案名稱：counter.vhd
--功能：可選擇不同計數頻率之三位元上數計數器
------------------------------------------------------------------------------
　

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity counter is
port (
clk1 : in std_logic;
clk2 : in std_logic;
clk3 : in std_logic;
clk4 : in std_logic;
sel : in std_logic_vector(3 downto 0);
cnt : out std_logic_vector (2 downto 0) --3 bits
);
end counter;

architecture arch of counter is
signal clk: std_logic;
signal cnt1 : std_logic_vector(2 downto 0);
begin

-----------PROGRAM BODY-----------------------------------------------------
process (sel,clk1,clk2,clk3,clk4)
begin
case sel is
when "0111" => clk <= clk1;
when "1011" => clk <= clk2;
when "1101" => clk <= clk3;
when "1110" => clk <= clk4;
when others => clk <= '0';
end case;
end process;

process(clk)
begin
if clk'event and clk='1' then
cnt1<=cnt1+1;
end if;
end process;
cnt<=cnt1;
end arch;

------------------------------------------------------------------------------
--實驗名稱：輸出為低電位動作之3 to 8解碼器電路實習
--檔案名稱：bin2led.vhd
--功能：輸出為低電位動作之3 to 8解碼器電路描述
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

----------------------------------------------------------------------------
entity bin2led is
port (
bin : in std_logic_vector (2 downto 0); --3 bits
led : out std_logic_vector (7 downto 0) --8 leds
);
end bin2led;

architecture arch of bin2led is
begin

-----------PROGRAM BODY-----------------------------------------------------
process (bin)
begin
case bin is
when "000" => led <= "11111110"; -- 0 active low
when "001" => led <= "11111101"; -- 1
when "010" => led <= "11111011"; -- 2
when "011" => led <= "11110111"; -- 3
when "100" => led <= "11101111"; -- 4
when "101" => led <= "11011111"; -- 5
when "110" => led <= "10111111"; -- 6
when "111" => led <= "01111111"; -- 7
when others => led <= "11111111";
end case;
end process;

-----------------------------------------------------------------------------------------------
--實驗名稱：主程式
--檔案名稱：clk_div_led.vhd
--功能：完成除頻器、計數器和解碼器各電路方塊腳位對應連線
-----------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_div_led is
port (
clk : in std_logic; -- 1.8432 MHz
sel : in std_logic_vector(3 downto 0);
led : out std_logic_vector(7 downto 0)
);
end clk_div_led;

architecture arch of clk_div_led is

---------COMPONENT DECLARED----------------------------------------------------

component clk_div
generic(divisor:integer:=230400);
port(
clk_in : in std_logic;
clk_out8Hz: buffer std_logic;
clk_out4Hz: buffer std_logic;
clk_out2Hz: buffer std_logic;
clk_out1Hz: buffer std_logic
);
end component;

component counter
port (
clk1 : in std_logic;
clk2 : in std_logic;
clk3 : in std_logic;
clk4 : in std_logic;
sel : in std_logic_vector(3 downto 0);
cnt : out std_logic_vector (2 downto 0) --3 bits
);
end component;

component bin2led
port (
bin : in std_logic_vector (2 downto 0); --3 bits
led : out std_logic_vector (7 downto 0) --8 leds
);
end component;
---------SIGNAL DECLARED----------------------------------------------------
signal clk1,clk2,clk3,clk4 : std_logic;
signal bin: std_logic_vector(2 downto 0);

begin

u1: clk_div port map(clk,clk1,clk2,clk3,clk4);
u2: counter port map(clk1,clk2,clk3,clk4,sel,bin);
u3: bin2led port map(bin,led);

end arch;

--------------------------------------------------------------------
--實驗名稱：電子琴實習
--檔案名稱：music.vhd
--功能：SW1 -> Do, SW2 -> Rai
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity music is
port(
clk : in std_logic;
sel : in std_logic_vector(1 downto 0);
music_out : out std_logic
);
end music;

architecture arch of music is

component clk_div_music
generic(divisor:integer:=8);
port(
clk_in : in std_logic;
clk_out: out std_logic
);
end component;

signal clk1,clk2: std_logic;

begin

u1: clk_div_music
generic map(7045) --Do 261.6Hz 1.8432M->7045
port map(clk,clk1);
u2: clk_div_music
generic map(6275) --Rai 293.7Hz 1.8432M->6275
port map(clk,clk2);

---------- process ---------
process (sel,clk1,clk2)
begin
case sel is
when "01" => music_out <= clk1; --SW1 -> Do
when "10" => music_out <= clk2; --SW2 -> Rai
when others => music_out <= '0';
end case;
end process;

end arch;

---------------------------------------------------------------------------------------------
--實驗名稱：Moore狀態機計數器
--檔案名稱：state_counter.vhd
--功能：控制Do,Rei,Mi,Fa,So,La,Si,Do等音調選擇的多工器輸入
---------------------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY state_counter IS
PORT (clock : IN std_logic;
sel : OUT std_logic_vector(3 downto 0));
END state_counter;

ARCHITECTURE a OF state_counter IS
TYPE state IS ( S0, S1, S2, S3, S4, S5, S6, S7,S8, S9, S10, S11, S12);
SIGNAL present_state, next_state : state;
BEGIN

state_comp:PROCESS (present_state)
BEGIN

CASE present_state IS
WHEN S0 =>
sel<="0101";
next_state <= S1;
WHEN S1 =>
sel<="0011";
next_state <= S2;
WHEN S2 =>
sel<="0011";
next_state <= S3;
WHEN S3 =>
sel<="0100";
next_state <= S4;
WHEN S4 =>
sel<="0010";
next_state <= S5;
WHEN S5 =>
sel<="0010";
next_state <= S6;
WHEN S6 =>
sel<="0001";
next_state <= S7;
WHEN S7 =>
sel<="0010";
next_state <= S8;
WHEN S8 =>
sel<="0011";
next_state <= S9;
WHEN S9 =>
sel<="0100";
next_state <= S10;
WHEN S10 =>
sel<="0101";
next_state <= S11;
WHEN S11 =>
sel<="0101";
next_state <= S12;
WHEN S12 =>
sel<="0101";
next_state <= S0;

END CASE;
END PROCESS state_comp;

state_clocking :PROCESS (clock)
BEGIN
IF clock'event and clock='1' THEN
present_state <= next_state ;
END IF ;
END PROCESS state_clocking;

END a;

---------------------------------------------------------------------------------------
--實驗名稱：音調產生器
--檔案名稱：music_gene.vhd
--功能：產生Do,Rei,Mi,Fa,So,La,Si,Do等音調的頻率產生器設計
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity music_gene is
port(
clk : in std_logic;
clk1,clk2,clk3,clk4,clk5,clk6,clk7,clk8 : out std_logic
);
end music_gene;

architecture arch of music_gene is

component clk_div_music
generic(divisor:integer:=8);
port(
clk_in : in std_logic;
clk_out: out std_logic
);
end component;

begin

u1: clk_div_music
generic map(38226) --Do 261.6Hz
port map(clk,clk1);
u2: clk_div_music
generic map(34048) --Rai 293.7Hz
port map(clk,clk2);
u3: clk_div_music
generic map(30339) --Mi 329.6Hz
port map(clk,clk3);
u4: clk_div_music
generic map(28638) --Fa 349.1Hz
port map(clk,clk4);
u5: clk_div_music
generic map(25510) --so 392.0Hz
port map(clk,clk5);
u6: clk_div_music
generic map(22727) --La 440.0Hz
port map(clk,clk6);
u7: clk_div_music
generic map(20275) --si 493.2Hz
port map(clk,clk7);
u8: clk_div_music
generic map(19109) --Do 523.3Hz
port map(clk,clk8);
end arch;

---------------------------------------------------------------------
--實驗名稱：掃描式多工顯示之兩位數BCD計數器
--檔案名稱：up_scan_top.vhd
--功能：掃描式多工顯示之兩位數BCD計數器
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------------------------------------------
--DESCRIPTION : led8 and 7segment test with scan and up counter function top level
--FILE NAME : u_d_scan_top.vhd
---------------------------------------------------------------------------
entity up_scan_top is
port (
clk : in std_logic; -- 1.8432 MHz
rst_n : in std_logic;
ce : in std_logic;
led_en : in std_logic;
seg_en : in std_logic;
led : out std_logic_vector(7 downto 0);
seg_out : out std_logic_vector(6 downto 0);
seg_one_en: out std_logic;
seg_ten_en: out std_logic
);
end up_scan_top;

architecture arch of up_scan_top is

---------COMPONENT DECLARED----------------------------------------------------
---------clk_div 1hz 64hz component----------
component clk_div_1_64
port(
clk_in : in std_logic;
clk_out1: out std_logic;
clk_out2: out std_logic
);
end component;

---------up_counter_4_10 component----------
component up_counter4_10
port(
clk : in std_logic; --system clock
rst_n : in std_logic; --reset
ce : in std_logic; --chip enable
q_one : out std_logic_vector(3 downto 0); --counter one output
q_ten : out std_logic_vector(3 downto 0) --counter ten output
);
end component;

---------binary to 7segment decoder---------
component bin2seg0_scan
port (
clk : in std_logic; --64hz clock
seg_en : in std_logic; --segment enable
q_one : in std_logic_vector(3 downto 0);
q_ten : in std_logic_vector(3 downto 0);
seg_out : out std_logic_vector(6 downto 0);
seg_one_en: out std_logic;
seg_ten_en: out std_logic
);
end component;

---------binary to led8 decoder---------
component bin2led0_10
port (
led_en : in std_logic; --led enable
bin : in std_logic_vector (3 downto 0); --4 bits
led : out std_logic_vector (7 downto 0) --8 leds
);
end component;

---------SIGNAL DECLARED----------------------------------------------------
signal clk_1hz : std_logic;
signal clk_64hz: std_logic;
signal q_one: std_logic_vector(3 downto 0);
signal q_ten: std_logic_vector(3 downto 0);

begin

----------Frequency divider----------
u1: clk_div_1_64 port map (clk, clk_1hz, clk_64hz);

----------4 bit up counter----------
u2: up_counter4_10 port map (clk_1hz, rst_n, ce, q_one, q_ten);

----------binary to LED decoder----------
u3: bin2led0_10 port map (led_en, q_one, led);

----------binary to seven segment decoder----------
u4: bin2seg0_scan port map (clk_64hz, seg_en, q_one, q_ten, seg_out,
seg_one_en, seg_ten_en);

end arch;